This application relies for priority upon Korean Patent Application No. 2002-20931, filed on Apr. 17, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor devices and, in particular, to a semiconductor chip package with direction-flexible mountability which can always operate normally regardless of the mounting direction when the semiconductor chip package is mounted onto a substrate.
In general, a semiconductor chip package comprises a package body made of epoxy molding resin and a plurality of leads protruding from the package body for external connection. The semiconductor chip package can be classified according to the configuration of the leads, for example, SIP (Single Inline Package), DIP (Dual Inline Package) and QFP (Quad Flat Package). The leads are arranged along opposing sides or all four sides of the package. The conventional semiconductor chip package is described below.
FIG. 1 illustrates a pin configuration of a conventional semiconductor chip package. FIG. 2 is a schematic logic diagram of the semiconductor chip package shown in FIG. 1. FIG. 3 is a functional block diagram of the semiconductor chip package shown in FIG. 1.
Referring to FIGS. 1 to 3, the conventional semiconductor chip package 130 is an eighteen-pin memory device in which leads 150 for external connection are aligned in the direction of the longer sides of a rectangular package body 140. Each lead 150 is specified by a pin number that has an inherent function. The first to seventh leads are address pins numbered in order A6, A5, A4, A3, A0, A1 and A2, respectively. An eighth lead is a chip. select pin (/CS). A ninth lead is a ground pin (GND). A tenth lead is a write enable pin (/WE). The eleventh to fourteenth leads are input/output pins (I/04 to I/01), respectively. The fifteenth to seventeenth leads are also address pins (A9 to A7), respectively. And, an eighteenth lead is a power supply pin (VCC). The ground pin (GND) is rotation-symmetrical to the power supply pin (VCC). The semiconductor chip package 130 further has an index pin 145 (hereinafter referred to as an ID pin) on the package body 140 so as to indicate the first lead.
The conventional semiconductor chip package must be aligned in the direction in which the semiconductor chip package is mounted onto a substrate. Because each lead has a fixed function, the circuit of the substrate should be consistent with the pin function and the semiconductor chip package should be mounted onto the substrate in a predetermined direction for a normal operation. If the circuit of the substrate is inconsistent with the mounting direction of the package, the semiconductor chip package does not operate normally. The basis of direction is the power supply pin (VCC) and the ground pin (GND). For correct alignment, the package body 140 has the ID pin 145 so that the user can easily recognize the first lead.
Therefore, the conventional semiconductor chip package has some disadvantages due to the limitation of direction. First, it requires an index marking process for indicating the mounting direction of the package or the position of the first lead. It also requires a test process including a visual inspection for guaranteeing correct placement of the index mark. Second, it requires continuous attention to the correct lead position and watchfulness throughout the package assembly process. Third, even if the proper direction is completely assured, the conventional method further requires guarantees of correct pin configuration in the substrate fabrication process. Additionally, it requires guarantees of the proper mounting direction during handling and transportation of materials for inventory management, along with the resultant extra human resources involved in such operations.
Accordingly, an object of the present invention is to provide a semiconductor chip package which can operate normally regardless of the mounting direction of a package upon a substrate.
Another object of the present invention is to provide a semiconductor chip package which eliminates the index process for indicating an ID pin.
In order to achieve the foregoing and other objects, the present invention provides a semiconductor chip package comprising a switching circuit for switching a pin function according to the mounting direction of the package, a pair of pin definition leads for defining the pin function, a pair of power supply leads, and a pair of ground leads.
It is preferred that the pin definition leads are aligned with the power supply leads, and that the power supply leads are disposed at the outermost edge of a row of leads. One of the power supply lead pair, the ground lead and the pin definition lead, is rotation-symmetrical to the other. That is, as the mounting direction of the package rotates by 90 or 180 degrees, one of these lead pairs may correspond to the other.
The semiconductor chip package in accordance with the present invention may be DIP (Dual Inline Package), QFP (Quad Flat Package), BGA (Ball Grid Array) or SIP (Single Inline Package). It is preferred that the semiconductor chip package of the present invention is applied to memory devices having address pins, input/output pins, control pins, power supply pins and ground pins.